As it is known, and as shown schematically in FIG. 1, a memory cell 1, of the floating-gate type, of a non-volatile memory device, for example of a flash type, generally comprises: a bulk region 2, for example, with a p-type doping, provided in a substrate 3 of semiconductor material, for example silicon; a source region 4 and a drain region 5, for example with a n-type doping, provided within a surface portion of the bulk region 2; a floating-gate region 6, arranged above the bulk region 2 and separated from the same bulk region 2 by a tunnel-oxide region 7; and a control-gate region 8, arranged above the floating-gate region 6 and separated therefrom by an intermediate oxide (the so-called “ONO”) region 9.
For storing information, electric charges are injected from the substrate 3 into the floating-gate region 6 (program operation), thus varying the threshold of the memory cell 1, i.e., the voltage to be applied between the control-gate region 8 and the source region 4 to switch-on the memory cell 1 and obtain conduction of electric current between the source region 4 and the drain region 5.
The reading operation, upon application of an appropriate biasing voltage to the control-gate region 8, detects the conduction characteristic of the memory cell 1, from which it is possible to obtain the stored information.
The erase operation for erasing the information envisages removal of the electric charge stored in the floating-gate region 6, via electron extraction. In particular, this operation envisages (as illustrated in FIG. 1) application of a high electrical field between the bulk region 2, which is brought to a high voltage of a positive value (for example +10 V), and the control-gate region 8, which is brought to a high voltage of a negative value (for example −10 V). In a known manner, the high electrical field that is generated is such as to trigger the FN tunneling effect, which causes movement of the electrons, which migrate from the floating-gate region 6 through the tunnel-oxide region 7 (once again, as illustrated schematically in FIG. 1).
In particular, in a known manner, the erase operations are generally carried out simultaneously on a set of memory cells 1, belonging for example to a same block, sector, or page, of the non-volatile memory device, these cells being thus erased together in a same erase operation.
Evidently, the erase process is effective only if the applied electrical field has a value sufficient to trigger the FN tunneling effect.
On account of the natural process of degradation of the memory cells 1 (for example, due to charge trapping in the tunnel-oxide region 7), this value, however, increases as the so-called “cycling” (i.e., the number of program/erase cycles undergone by the same memory cells 1) increases.
In order to take into account this degradation phenomenon, an algorithm commonly used for carrying out the erase operation on a set (sector or page) of memory cells 1 envisages iterative application of a certain number of pulses, of an increasing voltage value and of a fixed duration, each followed by a verify operation for verifying that erase has been successful. The method is interrupted as soon as the verify operation determines that erase has been correctly performed.
This erase algorithm is illustrated schematically in FIG. 2, which shows the plot, with pulses of increasing value, of the bulk voltage Vpp, with the control-gate region 8 negatively selected (i.e., set at a voltage VCG of a high negative value, for example −10 V). As previously mentioned, the potential difference between the bulk region 2 and the control-gate region 8 determines the electrical field designed to trigger the FN tunneling effect.
The pulses of the bulk voltage Vpp start from a minimum value Vpp_min, determined in the stage of design or characterization of the non-volatile memory device, and increase, with constant steps, up to a maximum value Vpp_max, which is also determined during design or characterization of the memory device. Between successive pulses, the algorithm envisages a verify step, through a reading operation, to verify that erase has been successful.
If the verification does not yield a positive result, a subsequent pulse is iteratively applied, with an incremented value; otherwise, when it is verified that erase has been successful (i.e., when it is verified that the value of electrical field required for activation of the FN tunneling effect has been reached or crossed, as shown once again in FIG. 2) the process ends.
The envelope of all the pulses applied (represented with a dashed line) determines the slope with which the erase operation is carried out, i.e., the variation in time of the electrical field applied to the memory cells 1, and the rate at which the electrical field reaches and/or crosses the value required for activation of the FN tunneling effect. In a known way, this slope must not be too high in order to prevent excessive stresses on the memory cells 1; this slope thus has an impact on the duration of the erase operation.
As indicated previously, as the number of program/erase cycles carried out on the memory cells 1 increases, the value of electrical field required for activation of the FN tunneling effect increases, so that the number of pulses required for reaching effective erase of the memory cells 1 also increases, with consequent increase in the overall duration of the erase operation.
As indicated schematically in FIG. 3, as cycling increases, the number of pulses that are required by the erase operation increases accordingly: in the example, from one or two pulses required for erasing memory cells with cycling lower than 10 Kc or 50 Kc, to a number N−1 or N of pulses (with N for example equal to 10) required for erasing memory cells with cycling of 450 Kc or 500 Kc.
Considering a constant duration Tpulse for the various pulses, the time required for the erase operation is thus short for cells with low cycling, but may become very long for cells with high cycling, possibly becoming incompatible with certain applications of the memory device (in which, for example, a high response rate or, in any case, a pre-set response time substantially constant over time is required).